An optimized implementation architecture for the Kuwahara filter

This paper proposes an efficient and optimized architecture for the hardware implementation of the Kuwahara filter, which is used for edge-preserving noise removal of images. The algorithmic strength of the Kuwahara algorithm has been greatly reduced by various optimizations in the variance computation. A hybrid serial-parallel architecture is designed which takes advantage of the proposed optimizations. This results in a time and hardware efficient architecture. A comparative study of the proposed and traditional implementation has been done to demonstrate the efficacy of the architecture.