Enhancement of Production Pattern Development Methodology and Best Practices

Execution and stabilization of production patterns on ATE (Automatic Test Equipment) is becoming a challenging task with the increasing complexity of SoC(s)(System on chip). The conventional approach for production pattern development involves coding of test in HDL/HVL (e.g. system verilog), running the simulation at RTL level (or gate level netlist) to generate the vcd (Value Change Dump). The vcd is then converted to tester specific format to run on ATE/Virtual Tester. Many times these patterns go through regeneration process in order to stabilize across PVT (Process, Voltage, Temperature). E-fuse & MBIST production patterns take considerable time on ATE especially for SoC which have large number of electronic fuses (e.g. 1024 bits or more) & memories. Some of these patterns gate the start of post-silicon validation. With conventional methodology, the major challenges are the pattern generation time (it involves extensive usage of compute resources), inability to modify on the fly and information exchange across teams. To address the above challenges, we have developed a methodology (“scenario”) for fuse/MBIST patterns which eliminates vcd generation and enables on the fly tweaking and re-use. The patterns implemented with this approach, is re-usable across SoC(s) for BIST and e-fuse. In this paper, we will discuss this methodology and its impact. In applying this methodology, we have seen significant reduction on pattern bring-up time (~80%), silicon bring-up time (~80%) and pattern iteration count (<;2.6%) in C293 [1]. In addition, we will highlight some of the best practices followed as part of production pattern development, which helped us to reduce product characterization cycle by ~ 30% for C293 [1].