A formal model of several fundamental VHDL concepts

Author

Goldschlag, David M.

Author_Institution

Naval Res. Lab., Washington, DC, USA

fYear

1994

fDate

27 Jun-1 Jul 1994

Firstpage

177

Lastpage

181

Abstract

This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are proposed including nondeterministic assignments and unbounded asynchrony. Nondeterminism allows the specification of environments and of classes of devices. This model naturally captures the meaning of composition of VHDL programs

Keywords

delays; formal specification; specification languages; VHDL; concurrent statements; delta delays; formal model; hierarchical component structuring; nondeterministic assignments; resolution functions; semantics; unbounded asynchrony; Circuit simulation; Computational modeling; Computer languages; Delay; Discrete event simulation; Hardware design languages; Laboratories; Logic devices; Timing; US Department of Defense;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Assurance, 1994. COMPASS '94 Safety, Reliability, Fault Tolerance, Concurrency and Real Time, Security. Proceedings of the Ninth Annual Conference on

Conference_Location

Gaithersburg, MD

Print_ISBN

0-7803-1855-2

Type

conf

DOI

10.1109/CMPASS.1994.318454

Filename

318454

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2014648