DocumentCode
2015252
Title
Dynamic base register caching: a technique for reducing address bus width
Author
Farrens, Matthew ; Park, Arvin
Author_Institution
University of California
fYear
1991
fDate
1991
Firstpage
128
Lastpage
137
Keywords
Bandwidth; Computer science; Distributed computing; Integrated circuit technology; Machinery; Permission; Pins; Registers; Throughput; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 1991. The 18th Annual International Symposium on
Print_ISBN
0-89791-394-9
Type
conf
DOI
10.1109/ISCA.1991.1021606
Filename
1021606
Link To Document