DocumentCode
2015804
Title
The effect on RISC performance of register set size and structure versus code generation strategy
Author
Bradlee, David G. ; Eggers, Susan J. ; Henry, Robert R.
Author_Institution
Uuiversity of Washington
fYear
1991
fDate
1991
Firstpage
330
Lastpage
339
Keywords
Computer science; Contracts; Coprocessors; Delay; Performance loss; Permission; Pipelines; Processor scheduling; Reduced instruction set computing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 1991. The 18th Annual International Symposium on
Print_ISBN
0-89791-394-9
Type
conf
DOI
10.1109/ISCA.1991.1021625
Filename
1021625
Link To Document