Title :
Bias-temperature degradation of pMOSFETs: mechanism and suppression
Author :
Makabe, Mariko ; Kubota, Taishi ; Kitano, Tomohisa
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
We investigated pMOSFET Bias-Temperature (BT) degradation by using carrier separation analysis. Electrons tunneling from gate electrode to substrate were found to cause impact ionization at the SiO2/Si interface and result in the creation of trapped charges and interface states. A higher-concentration boron incorporation into the SiO2 film was found to suppress BT degradation. This is considered to be a result of tunneling electron current suppression. Degradation due to BT can also be suppressed by reducing the electric field in the oxide between the gate electrode and drain. In other words, BT degradation is lower for the ON-state than the OFF-state. The electric field between the gate electrode and drain can also be reduced by changing the side wall formation process
Keywords :
MOSFET; impact ionisation; interface states; ion implantation; rapid thermal annealing; semiconductor device reliability; tunnelling; 10 s; 2.6 to 8 nm; 900 to 1100 C; SiO2/Si interface; SiO2:B-Si; annealing temperature; bias-temperature degradation; carrier separation analysis; electron tunneling; gate oxide thickness; high-concentration B incorporation; impact ionization; interface states; oxide electric field; pMOSFETs; reliability threat; side wall formation process; trapped charges; tunneling electron current suppression; Boron; Degradation; Electrodes; Electrons; MOSFETs; Stress; Substrates; Temperature; Tunneling; Voltage;
Conference_Titel :
Reliability Physics Symposium, 2000. Proceedings. 38th Annual 2000 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-5860-0
DOI :
10.1109/RELPHY.2000.843916
