Effective thermal conductivity model for TSVs with insulation layer as contact resistance

Device scaling and heterogeneous integration necessitate through silicon vias (TSVs) as interconnects for 2.5D and 3D chip packages for shortened signal transmission, less delay, and more functionality. Proper evaluation of the thermal properties of TSVs is a key to the successful design of the package. On the other hand, the determination of in-plane thermal conductivity is complicated with the thin insulation materials made of silicon oxide or polymers surrounding the TSV, which is not well addressed in previous studies. In the present work, effort is made to develop a closed-form effective thermal conductivity model for the TSV array by treating the insulation material as the contact resistance. The present model takes into account the sizes and thermal conductivities of the constituents, which is able to predict the in-plane thermal conductivity with reasonable agreement in comparison with the numerical computation. Furthermore, the effect of the transverse heat conduction is examined in a package with a thermal test die on a silicon interposer and substrate. The numerical computation shows that, by taking into account the effect of insulation material, the package thermal resistance could increase by 7.3%.