Title :
Design and implementation of an ordered memory access architecture
Author :
Sriram, S. ; Lee, E.A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The authors describe a multiprocessor machine for real-time digital signal processing that uses commercial programmable DSP chips. The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled. The design is based on the architecture proposed by J.C. Bier and the authors (1990). A prototype has been built. The implementation details and performance results are discussed.<>
Keywords :
digital signal processing chips; parallel architectures; real-time systems; shared memory systems; DSP chips; design; implementation; multiprocessor machine; ordered memory access architecture; prototype; real-time digital signal processing; shared memory; single shared bus parallel processor;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on
Conference_Location :
Minneapolis, MN, USA
Print_ISBN :
0-7803-7402-9
DOI :
10.1109/ICASSP.1993.319126
