High-speed arithmetic coder/decoder architectures

The authors combine the techniques of interval tree search, look-ahead and redundant arithmetic to design high-speed architectures for arithmetic decoders. The decoder can be modeled as a FSM (finite state machine), enabling the application of the look-ahead technique to achieve higher speeds. The look-ahead approach leads to slight degradation in performance (in terms of the adder/subtractor delay in the coder/decoder due to increased word lengths). The performance of the decoder is improved by using redundant arithmetic. The tree search method combined with redundant arithmetic and look-ahead leads to desired speedups without any degradation in performance.<>