Title :
High speed merged multiplication
Author :
Islam, Farhad F. ; Tamaru, Keikichi
Author_Institution :
Dept. of Electron., Kyoto Univ., Japan
Abstract :
The authors propose a hardware algorithm for merged array multiplication. It offers an impressive improvement in latency when compared with a conventional scheme for merged array multiplication. The cost in the form of additional VLSI area is rather small and decreases with increasing bit-size of operands.<>
Keywords :
VLSI; array signal processing; digital arithmetic; digital signal processing chips; merging; VLSI area; hardware algorithm; latency; merged array multiplication;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on
Conference_Location :
Minneapolis, MN, USA
Print_ISBN :
0-7803-7402-9
DOI :
10.1109/ICASSP.1993.319134
