DocumentCode :
2017592
Title :
Advanced π-FET Technology for 45 nm Technology Node
Author :
Yi-Chuen Eng ; Jyi-Tsong Lin
Author_Institution :
Nat. Sun Yat-Sen Univ., Kaohsiung
fYear :
2007
fDate :
11-13 July 2007
Abstract :
In this study, the enhancement of pi-FET performance using optimized parameters is designed to investigate the electrical characteristics as a function of the BOI length (LBOI) under the body region. Additionally, the SOI devices (FDSOI-FET and UTBSOI-FET) are also designed for the comparison with the pi-FET by using ISE TCAD tools.
Keywords :
CAD; field effect transistors; semiconductor device models; silicon-on-insulator; BOI length; FDSOI-FET; ISE TCAD tools; SOI devices; UTBSOI-FET; electrical characteristics; performance enhancement; pi-FET technology; size 45 nm; CMOS integrated circuits; CMOS technology; Impact ionization; Integrated circuit reliability; MOSFETs; Materials reliability; Planarization; Rapid thermal annealing; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-1014-9
Type :
conf
DOI :
10.1109/IPFA.2007.4378081
Filename :
4378081
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2017592
بازگشت