Low power consumption and fast settling frequency synthesizer for TDMA-TDD systems

A novel configuration for a low power consumption, fast settling frequency synthesizer is presented. The synthesizer employs two sets of a sample-hold voltage-controlled oscillator (VCO) and a carrier switch which selects VCO output as the output of the synthesizer burst-by-burst. The frequency settling time of the synthesizer is drastically reduced below a few nanoseconds. The power consumption is less than 65% of that of the conventional synthesizer with dual phase locked loop (PLL) circuits. The frequency error caused by the sample-hold circuit is analyzed theoretically and experimentally. The results confirm that the theoretical analyses give a good approximation and show that the longer acquisition time of the sample-hold circuit minimizes the frequency error at the synthesizer output