VLSI architectures for recursive median filters

High sample rate array architectures, stack filter-based architectures, and sorting network-based architectures for computing recursive median filters are presented. The author develops nonpipelined architectures with lower sample periods than previous architectures, and then reduces the sample period further by pipelining. Pipelining is achieved by developing recursive algorithms that have additional delays in the feedback paths, and using the delays as pipeline latches. It is shown that for two levels of pipelining, the sample period of the array and stack filter-based architectures reduces by a factor of 2; the sample period is not, however, reduced proportionately for higher levels of pipelining because of the large implementation overhead. The sample period of sorting network-based architectures, however, can be reduced to any level for most-significant-bit-first implementations.<>