Area efficient VLSI architectures for Huffman coding

The authors present simple and area efficient VLSI architectures for Huffman coding, an industrial standard proposed by MPEG, JPEG, and others. They use a memory of size O(n log n) to store a Huffman code tree, where n is the number of symbols. It requires few simple arithmetic operations on the chip for real-time encoding and decoding. Based on the scheme, a design for 8-b symbols is presented. The proposed design requires 256*9 and 64*18-b memory modules to process 8-b symbols. The chip occupies a silicon area of 3.5*3.5 mm/sup 2/ using 1.2- mu m CMOSN standard library cells. Compared with the parallel implementation of A. Mukherjee et al. (1991), which requires up to 65536 processing element (PEs), the proposed architecture leads to a single PE design.<>