Designing on FPGA for Improved Performance

The area of field programmable gate array (FPGA) design is evolving at a rapid pace. Advancements in the complexity of the FPGA´s architecture mean that now it can be used in far more applications than before. This paper presents synthesis process, synthesis algorithm requirements and various other design improvements which in a true sense enhance the digital system performance with respect to area and delay trade offs. It also covers a number of timing issues that are important in basic digital system design. The issues are normally observed while working with Xilinx FPGAs. Some established techniques are reviewed relative to these criteria to understand their applicability and the potential for further research in these specialized areas