Title :
The Failure Mode Investigation of Barrier Layer TaN Combined with Al Pad Architecture using in Cu Process
Author :
Po-Ying Chen ; Shen-Li Chen ; Ming-Hsiung Tsai ; Jing, M.H. ; Lin, Tzu-Chiao
Author_Institution :
I-Shou Univ., Kaohsiung
Abstract :
CMOS chips are scaled to smaller geometries, the interconnects play an increasing role in the overall chip performance. This paper presents an integrated process for yield enhancement strategy to overcome a so-called "cosmetic defects" in 130- and 90-nm complementary metal-oxide-semiconductor (CMOS) process node.
Keywords :
CMOS integrated circuits; aluminium; copper; integrated circuit interconnections; integrated circuit yield; nanoelectronics; tantalum compounds; CMOS chips; CMOS process; TaN-Cu-Al; TaN-Cu-Al - Interface; barrier layer; chip performance; cosmetic defects; integrated circuit interconnects; integrated process; pad architecture; size 130 nm; size 90 nm; yield enhancement; CMOS process; Chip scale packaging; Copper; Delay; Dry etching; Electronic mail; Geometry; Manufacturing processes; Ultra large scale integration; Wiring; CMOS; Copper process; barrier metal; cosmetic defects; dry etching;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2007. IPFA 2007. 14th International Symposium on the
Conference_Location :
Bangalore
Print_ISBN :
978-1-4244-1014-9
DOI :
10.1109/IPFA.2007.4378097
