Double quadrature harmonic rejection architecture insensitive to gain and phase mismatch for analog/digital TV tuner IC

Author

Ryu, Jaeyoung ; Cho, Seungwoo ; Lee, Jeongsu ; Kim, Jongjin ; Ku, Yeonwoo ; Kwon, Kuduck ; Kang, Hyunkoo

Author_Institution

DMC R&D Center, Samsung Electron., Suwon, South Korea

fYear

2011

fDate

5-7 June 2011

Firstpage

1

Lastpage

4

Abstract

Image rejection and harmonic rejection are important performance parameters in wideband low-IF TV system. In this paper, double quadrature harmonic rejection architecture insensitive to gain and/or phase mismatch is proposed to satisfy stringent image rejection ratio (IRR) and harmonic rejection ratio (HRR) for analog/digital TV tuner ICs. Fabricated in 0.13μm CMOS process, more than 60dB of the IRR is achieved over 42-864MHz RF frequency and more than 69dB of the 3rd HRR is achieved over 42-306MHz RF frequency without any calibration.

Keywords

CMOS integrated circuits; cable television; tuning; CMOS process; IRR; analog-digital TV tuner IC; cable TV tuner; double quadrature harmonic rejection architecture; gain mismatch; image rejection ratio; phase mismatch; size 0.13 mum; wideband low-IF TV system; Band pass filters; Frequency measurement; Harmonic analysis; Mixers; Power harmonic filters; Radio frequency; Tuners; Si-Tuner; complex filter; harmonic rejection; harmonic rejection mixer; image rejection;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE

Conference_Location

Baltimore, MD

ISSN

1529-2517

Print_ISBN

978-1-4244-8293-1

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2011.5940674

Filename

5940674