A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs

Author

Titus, Ward S. ; Kenney, John G.

Author_Institution

Analog Devices, Somerset, NJ, USA

fYear

2011

fDate

5-7 June 2011

Firstpage

1

Lastpage

4

Abstract

A DCO is realized in 0.13μ CMOS using 4 cores for a 5.6 to 11.5 GHz octave tuning bandwidth to provide the clock for an all digital D/PLL CDR circuit. The DCO is novel in that it can track more than a 130 degree C temperature variation while the CDR maintains an error free lock to data. Each core is directly coupled to a div/2 to produce I/Q signals that a 4:1 MUX combines into a single set of 2.8 to 5.8 GHz quadrature outputs to drive the sine interpolator of the CDR. Locked to maximum data rms jitter, integrated from 1 kHz to 1 GHz is 299 fs @ 9.953 Gb/s (Sonet OC-192) from a DCO phase noise of -116 dBc/Hz at 1 MHz offset. The kDCO gain is 190 ppm/bit with less than 2:1 variation over the full BW. The combined DCO, divide by 2 and MUX current is 14 mA to 37 mA on a 1.2V regulated supply at 25C.

Keywords

CMOS integrated circuits; circuit tuning; clock and data recovery circuits; integrated circuit noise; interpolation; oscillators; phase locked loops; phase noise; varactors; CMOS; DCO; I/Q signal; all digital D/PLL CDR circuit; clock data recovery; current 14 mA to 37 mA; digital dual loop CDR; digitally controlled oscillator; error free lock; frequency 2.8 GHz to 5.8 GHz; frequency 5.6 GHz to 11.5 GHz; octave tuning bandwidth; phase noise; sine interpolator; size 0.13 mum; temperature 130 C; temperature 25 C; varactor; voltage 1.2 V; Arrays; Bandwidth; Jitter; Phase noise; Temperature distribution; Temperature measurement; Tuning; CMOS; DCO; DPLL; VCO; varactors;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE

Conference_Location

Baltimore, MD

ISSN

1529-2517

Print_ISBN

978-1-4244-8293-1

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2011.5940678

Filename

5940678