Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches

Author

Eliezer, Oren ; Staszewski, Bogdan ; Vemulapalli, Sudheer

Author_Institution

Xtendwave, Dallas, TX, USA

fYear

2011

fDate

5-7 June 2011

Firstpage

1

Lastpage

4

Abstract

A digitally-controlled oscillator (DCO) with a fully-digital compensation mechanism for mismatches in its frequency-tuning capacitor array is proposed. It addresses the inevitable mismatch between the smallest frequency step supported by the integer portion of the frequency-tuning array and the dithering-based fractional portion. Such mismatch results in modulation distortion during transmission and in potential violation of the transmitter´s modulation accuracy specifications. The presented solution, which is built-in and relies solely on digital logic and software, is implemented in a 65nm CMOS GSM/EDGE Digital RF Processor (DRP)-based transceiver.

Keywords

capacitors; cellular radio; phase locked loops; radio transceivers; radiofrequency oscillators; ADPLL; DCO; DRP; GSM-EDGE transceiver; built-in compensation; capacitor mismatch; digital RF processor-based transceiver; digital controlled oscillator; digital logic; dithering-based fractional portion; frequency-tuning capacitor array; size 65 nm; transmitter modulation distortion; Arrays; Capacitors; Frequency measurement; Frequency modulation; Oscillators; Tuning; ADPLL; DCO; DRP; mismatch compensation;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2011 IEEE

Conference_Location

Baltimore, MD

ISSN

1529-2517

Print_ISBN

978-1-4244-8293-1

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2011.5940709

Filename

5940709