• DocumentCode
    2020265
  • Title

    Digital arithmetic using analog arrays

  • Author

    Sadeghi-Emamchaie, Saeid ; Jullien, G.A. ; Dimitrov, V. ; Miller, W.C.

  • Author_Institution
    VLSI Res. Group, Windsor Univ., Ont., Canada
  • fYear
    1998
  • fDate
    19-21 Feb 1998
  • Firstpage
    202
  • Lastpage
    205
  • Abstract
    This paper describes techniques for using locally connected analog cellular neural networks (CNNs) to implement digital arithmetic arrays; the arithmetic is implemented using a recently disclosed Double-Base Number System (DBNS). The CNN arrays are targeted for low power low-noise DSP applications where lower slew rate during transitions is a potential advantage. Specifically, we demonstrate that a CNN array, using a simple nonlinear feedback template, with hysteresis, can perform arbitrary length arithmetic with good performance in terms of stability and robustness. The principles presented in this paper can also be used to implement arithmetic in other number systems such as the binary number system
  • Keywords
    analogue processing circuits; cellular neural nets; circuit stability; digital arithmetic; digital signal processing chips; analog arrays; arbitrary length arithmetic; digital arithmetic; double-base number system; locally connected analog cellular neural networks; low-noise DSP applications; nonlinear feedback template; robustness; slew rate; stability; Cellular neural networks; Digital arithmetic; Digital signal processing; Hysteresis; Large-scale systems; Neurofeedback; Nonlinear equations; Robust stability; Stability; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
  • Conference_Location
    Lafayette, LA
  • ISSN
    1066-1395
  • Print_ISBN
    0-8186-8409-7
  • Type

    conf

  • DOI
    10.1109/GLSV.1998.665226
  • Filename
    665226