Quality evaluation and simulation of through-multilayer TSV integration process for memory stacking

3D integration using through silicon via (TSV) has many advantages, such as high packaging density, small form factor and high bandwidth due to the short connection lengths. In this paper, a through-multilayer integration approach for memory module was proposed with the RDLs being fabricated using lift-off process prior to via filling. The stacking samples containing of 3 layers were prepared and all the 88 dies on the 4-inch wafer were measured. The average resistance of single layer Kelvin test structure was 1.54mΩ, with the lowest and highest measured values being 1.37mΩ and 1.69mΩ respectively. The quality of bonding strength has been characterized through shear tests, and the optimized bonding parameters have been put forward after a set of parameter combinations experiment. The average of shear strength increased by 6.44% after process optimization. The mean of bonding precision was 3.31µm, with the bonding yield being 94.17%, which meet the requirements of precision within 5µm. Thermodynamic simulation has been done to characterize the Mises stress and warping values of 3 layers TSV integration. All test results supported the good quality of this through-multilayer integration approach.