• DocumentCode
    2021266
  • Title

    Random self-test method applications on PowerPCTM microprocessor caches

  • Author

    Raina, Rajesh ; Molyneaux, Robert

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1998
  • fDate
    19-21 Feb 1998
  • Firstpage
    222
  • Lastpage
    229
  • Abstract
    This paper describes a novel method for generating test stimuli for digital systems. By taking advantage of certain properties of the Design Under Validation, the method can be used to generate test stimuli that are random as well as self-testing. We discuss the requirements and limitations of this method on practical designs. The use of this method for High-Level Design Validation of caches in PowerPCTM microprocessors is also described. The paper concludes by identifying areas where further work is needed
  • Keywords
    cache storage; design for testability; high level synthesis; integrated circuit testing; microprocessor chips; PowerPC; design under validation; high-level design; random self-test method applications; test stimuli; Automatic testing; Built-in self-test; Design engineering; Design methodology; Digital systems; Gold; Microprocessors; Power generation; State-space methods; System testing; Trademarks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
  • Conference_Location
    Lafayette, LA
  • ISSN
    1066-1395
  • Print_ISBN
    0-8186-8409-7
  • Type

    conf

  • DOI
    10.1109/GLSV.1998.665230
  • Filename
    665230
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2021266