Optimum bias for highly linear and efficient doherty power amplifier with memoryless digital predistortion

This paper investigates the optimum bias to achieve a highly efficient and linear Doherty power amplifier (DPA) with memoryless digital predistortion (DPD). The DPA is implemented using 25-W GaN HEMTs The PAE of 54.5% is achieved at an output power of 40 dBm for a 2.14-GHz continuous wave. The bias optimization and memoryless DPD are employed to improve the linearity of the DPA. The 11^th-memoryless polynomial and recursive least square algorithm are used to implement the memoryless DPD. For a one-carrier WCDMA signal at an output power of 36 dBm, the adjacent channel leakage ratio at ±5-MHz offset are below -48 dBc with the drain efficiency of 40% after the linearization with the optimum bias.