The thermal mechanical reliability induced by the integrated circuits fabrication process

This work mainly focuses on the thermal mechanical stability issues on the three dimensional thought silicon vias in the fabrication stage. The fabrication processes, including redistribution layer fabrication, baking glue and reflowing soldering, and filling under-fill are analyzed. With distinct thermal mismatches of the thought silicon vias Cu and SiO2, stress concentration induced by discontinuity of the model structure, and the high thermal gradient, the thought silicon vias Cu suffers sever thermal management problems and even the thermal failure. The fabrication processes not only lead high tensile press on some local area but also bring high compressive press in some region. Moreover, the compressive press in X direction (σx = −100 MPa) and tensile press in Y direction (σy = 109 MPa) work together at the inflection point of the TSVs and SiO2. The interaction of the two forms the normal stress is very interesting, and the thermal stability of the singularities has great different changing mechanism.