DocumentCode
2021551
Title
Analytical Performance of One-Step Majority Logic Decoding of Regular LDPC Codes
Author
Radhakrishnan, R. ; Sankaranarayanan, Sriram ; Vasic, B.
Author_Institution
Univ. of Arizona, Tucson
fYear
2007
fDate
24-29 June 2007
Firstpage
231
Lastpage
235
Abstract
In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.
Keywords
decoding; error correction codes; error statistics; parity check codes; bit error rate performance; combinatorial algorithm; error correction; logic decoding; low-density parity check codes; nano-scale memories; regular LDPC codes; Bit error rate; Circuit faults; Equations; Error correction; Geometry; Iterative algorithms; Iterative decoding; Logic gates; Parity check codes; Performance analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory, 2007. ISIT 2007. IEEE International Symposium on
Conference_Location
Nice
Print_ISBN
978-1-4244-1397-3
Type
conf
DOI
10.1109/ISIT.2007.4557231
Filename
4557231
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