The characterization of TSV Cu protrusion under thermal cycling

Three-dimensional (3D) integrated circuit (IC) technology is considered as the preferred More-than-Moore approach due to its capabilities of miniaturization, high density and multi-function. And through silicon via (TSV) is the key enabling technology of 3D integration. So now TSV is getting more and more attention. However, TSV manufacturing processes are still facing several challenges, one of which is known as TSV protrusion. This is a potential threat to the backend interconnect structure, since it can lead to cracking or delamination. In this work, we studied the behavior of TSV Cu protrusion under different thermal cycling numbers. The TSV Cu protrusion was measured with white light interferometry (WLI) of subnanometer scale. The results help to solve a key TSV-related manufacturing yield and reliability challenge.