DocumentCode
2022858
Title
Partially depleted CMOS SOI technology for low power RF applications
Author
Tinella, C. ; Gianesello, F. ; Gloria, D. ; Raynaud, C. ; Delatte, P. ; Engelstein, A. ; Fournier, J.M. ; Benech, Ph. ; Jomaah, J.
Author_Institution
FTM, STMicroelectronics, Crolles, France
fYear
2005
fDate
3-4 Oct. 2005
Firstpage
101
Lastpage
104
Abstract
The low resistivity substrate that is used in bulk silicon processes (CMOS and BiCMOS) limits the integration of high-quality passives components and gives rise to severe substrate coupling issues. This paper shows how to take advantage of HR SOI to improve RF circuit performances as well as the effectiveness of HR SOI to reduce substrate coupling. Potentiality of mm-wave passive integration is also shown.
Keywords
CMOS integrated circuits; passive networks; radiofrequency integrated circuits; silicon-on-insulator; substrates; BiCMOS; CMOS SOI technology; RF circuit; Si; bulk silicon processes; high-quality passives components; low power RF applications; mm-wave passive integration; substrate coupling; BiCMOS integrated circuits; CMOS process; CMOS technology; Conductivity; Coupling circuits; Inductors; Q factor; Radio frequency; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005. European
Conference_Location
Paris
Print_ISBN
88-902012-0-7
Type
conf
Filename
1637160
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