DocumentCode
2023063
Title
A GaAsSb/InP HBT circuit technology
Author
Godin, J. ; Riet, M. ; Konczykowska, A. ; Berdaguer, P. ; Kahn, M. ; Bove, P. ; Lahreche, H. ; Langer, R. ; Lijadi, M. ; Pardo, F. ; Bardou, N. ; Pelouard, J.-L. ; Maneux, C. ; Belhaj, M. ; Grandchamp, B. ; Labat, N. ; Touboul, A. ; Bru-Chevallier, C. ; C
Author_Institution
Thales III-V Lab, Alcatel, Marcoussis, France
fYear
2005
fDate
3-4 Oct. 2005
Firstpage
133
Lastpage
136
Abstract
A InP/GaAsSb/InP double-heterojunction bipolar transistor (DHBT) structure has been defined, realized by MBE epitaxy, and optimized, thanks to simulation based on in-depth physical characterizations. A circuit-oriented technology has been developed, which has been validated by the design and fabrication of a full-rate (40 GHz clock) 40 Gbit/s D-FF.
Keywords
III-V semiconductors; gallium arsenide; gallium compounds; heterojunction bipolar transistors; indium compounds; molecular beam epitaxial growth; 40 GHz; 40 Gbit/s; HBT circuit technology; InP-GaAsSb-InP; MBE epitaxy; circuit-oriented technology; double-heterojunction bipolar transistor structure; Circuit simulation; DH-HEMTs; Diffraction; Epitaxial growth; Fabrication; Heterojunction bipolar transistors; Indium phosphide; Lattices; Molecular beam epitaxial growth; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005. European
Conference_Location
Paris
Print_ISBN
88-902012-0-7
Type
conf
Filename
1637168
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