An approach to a high throughput matricial packet switch

Author

Lizcano, P.J. ; Chas, P.L. ; Jimenez, J.

Author_Institution

Telefonica Investigacion y Desarrollo, Madrid, Spain

fYear

1988

fDate

12-15 June 1988

Firstpage

604

Abstract

A fully-hardware-based packet switch design is presented. The main features of its architecture are the nonblocking and noncontention basis of its implementation, which provides a high throughput capability and a low (and limited for all traffic situations) internal time delay. The approach used for this system assumes the development of several custom ICs which perform simple packet processing algorithms, embedded in hardware, and also takes advantage of the fast static memories now on the market. This fast switching system functions in a highly parallel processing way, and is well suited to support voice and data integration.<>

Keywords

data communication systems; electronic switching systems; packet switching; parallel processing; voice communication; custom ICs; fast switching system; high throughput; internal time delay; matricial packet switch; nonblocking; noncontention; packet processing algorithms; parallel processing; static memories; voice and data integration; Communication switching; Data communication; Delay effects; Hardware; Packet switching; Parallel processing; Switches; Switching systems; Throughput; User interfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 1988. ICC '88. Digital Technology - Spanning the Universe. Conference Record., IEEE International Conference on

Conference_Location

Philadelphia, PA, USA

Type

conf

DOI

10.1109/ICC.1988.13635

Filename

13635