Noise parameter modeling and SiGe profile design tradeoffs for RF applications

Author

Guofu Niu ; Shiming Zhang ; Cressler, J.D. ; Joseph, A.J. ; Fairbanks, J.S. ; Larson, L.E. ; Webster, C.S. ; Ansley, W.E. ; Harame, D.L.

Author_Institution

Dept. of Comput. Eng., Auburn Univ., AL, USA

fYear

2000

fDate

28-28 April 2000

Firstpage

9

Lastpage

14

Abstract

This paper presents a unified approach to optimizing SiGe transistors for low noise. An intuitive model relating transistor structural parameters and biases to noise parameters is introduced, and used to identify the noise limiting factors in a given transistor technology. Issues related to the calibration of 2-D device simulation are discussed. SiGe profile design trade-offs for low noise performance are then presented with experimental results.

Keywords

Ge-Si alloys; UHF bipolar transistors; heterojunction bipolar transistors; microwave bipolar transistors; semiconductor device models; semiconductor device noise; semiconductor materials; 2D device simulation; RF applications; SiGe; SiGe HBT; SiGe profile design tradeoffs; SiGe transistors; low noise performance; noise limiting factors; noise parameter modeling; noise parameters; transistor biases; transistor structural parameters; Application software; Circuit noise; Design engineering; Design optimization; Germanium silicon alloys; Heterojunction bipolar transistors; Integrated circuit noise; Microelectronics; Radio frequency; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2000. Digest of Papers. 2000 Topical Meeting on

Conference_Location

Garmisch, Germany

Print_ISBN

0-7803-6255-1

Type

conf

DOI

10.1109/SMIC.2000.844285

Filename

844285