A new method for reducing warpage due to reflow in IGBT module

Warpage in Insulated Gate Bipolar Transistor (IGBT) module is induced by the unavoidable mismatch of materials and asymmetric structure in almost every packaging process. The high level of warpage and thermal stress is introduced during reflow processes, which can impact the IGBT reliability. Pre-warping substrate method has been used as industry practice for reducing warpage due to reflow. The method still faces challenges of low cost and process simplification. With the development of copper bonding technique, IBP (Integrate base plate) was recently developed for reducing the warpage. However, the method is not cost-effective. In this paper, a low-cost and simple method of embedding DBC plates into copper substrate has been proposed as alternative solution for the warpage reduction. A 1200V IGBT module prototype was selected for benchmarking the warpage reduction methods. Finite element method with viscoplastic solder model and large deformation theory was used to investigate the solder reflow process. Anand constitutive model available in FEM tools for modeling the viscoplastic behaviors of solder materials was used for SAC305 solder layers. The whole reflow process was simulated by advanced element “death and activation” technique. Three package assembly methods for reducing warpage were investigated by advanced finite element analyses. The FEA result shows that the proposed new method can effectively reduce the warpage of IGBT module to industry-acceptable level.