An 8-bit 42 Msamples/s current-mode folding and interpolation CMOS analog-to-digital converter with three-level folding amplifiers

Author

Kim, Kyung Myun ; Yoon, Kwang Sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

Volume

1

fYear

1996

fDate

18-21 Aug 1996

Firstpage

201

Abstract

A low power 8-bit current-mode folding and interpolation analog to digital converter (ADC) with three-level folding amplifiers is presented in this paper. A three-level folding amplifier is designed not only to reduce the number of reference current sources, but also to decrease power dissipation within the ADC. A newly designed delay time error correction circuit is employed to make delay time error correction between the coarse quantizer and the fine quantizer. The simulation results illustrate a conversion rate of 42 MSamples/s and a power dissipation of 30 mW

Keywords

CMOS analogue integrated circuits; CMOS integrated circuits; amplifiers; analogue-digital conversion; circuit analysis computing; delays; error correction; integrated circuit design; 1.5 mum; 30 mW; 8 bit; CMOS analog-to-digital converter; amplifier design; conversion rate; current-mode folding; delay time error correction circuit; interpolation; low power ADC; n-well CMOS technology; power dissipation; reference current sources; simulation results; three-level folding amplifiers; Analog-digital conversion; Circuits; Delay effects; Error correction; Interpolation; Power amplifiers; Power dissipation; Power engineering and energy; Signal processing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.594092

Filename

594092