Increasing resistance to differential power analysis attacks in reconfigurable systems

Nowadays, security is becoming the most critical factor in numerous application domains. At the same time, state-of-the-art FPGAs are frequently used in order to improve the performance of various embedded systems. In those systems the FPGAs usually execute, among others, certain encryption algorithms since it has been proved that they are very efficient when implementing such tasks. This paper presents a highly secure platform based on a common low-cost Xilinx FPGA. The security algorithm employed is AES-128 which is the most widely used such algorithm; one of the main drawbacks of this scheme is that it is vulnerable to a sophisticated family of attacks called differential power analysis (DPA) attacks. In order to heavily increase the resistance of our system to such attacks we propose a specific implementation methodology tailored to the characteristics of the FPGAs; as our real-world experiments clearly demonstrate our approach results to FPGA-based systems that are more than an order of magnitude more secure, when such attacks are considered, than the ordinary reconfigurable systems implementing the exact same encryption/decryption algorithm.