A novel design and successful simulation of QCA-based multiplexer

This paper presents the successful design and literal layout of a 4 to 1 multiplexer and simulation of a 8 to 1 multiplexer, by the five-inputs majority gate. This 4 to 1 multiplexer can be considered as a module, which has a fixed structure and the correct clocking. Multiplexer presented in this paper, that implemented with five inputs the majority gate, which has been designed with the minimum number of cells, also acts as a pipeline. The 4 to 1 multiplexer is used as modular, to implement the 2ⁿ to 1 multiplexer.