DocumentCode
2025537
Title
Use of test structures for Cu interconnect process development and yield enhancement
Author
Skumanich, Andy ; Ping Cai, Man ; Educato, J. ; Yost, Dennis
Author_Institution
Appl. Mater. Inc., Santa Clara, CA, USA
fYear
2000
fDate
2000
Firstpage
63
Lastpage
66
Abstract
A methodology is described where wafers with specialized test structures are inspected with wafer metrology tools to assist process development for Cu BEOL fabrication. A Cu damascene interconnect process is examined from oxide deposition to final electrical test and the defects are tracked. E-test prioritizes the defects by the electrical impact. The inspection and tracking of defects facilitates defect sourcing, assists root cause analysis, and allows for more effective corrective action to be implemented.
Keywords
copper; inspection; integrated circuit interconnections; integrated circuit testing; integrated circuit yield; BEOL fabrication; Cu; Cu damascene interconnect; defect sourcing; defect tracking; electrical test structure; inspection; oxide deposition; process development; root cause analysis; wafer metrology; yield enhancement; Automatic optical inspection; Fabrication; Geometry; Monitoring; Productivity; Shape; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on
Print_ISBN
0-7803-6275-7
Type
conf
DOI
10.1109/ICMTS.2000.844406
Filename
844406
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