A microelectronic test structure for signal integrity characterization in deep submicron technology

Author

Caignet, Fabrice ; Dhia, S.D.-B. ; Sicard, Eticnne

Author_Institution

Complexe Sci. de Rangueil, Inst. Nat. des Sci. Appliquees, Toulouse, France

fYear

2000

fDate

2000

Firstpage

67

Lastpage

71

Abstract

The benefits expected by the decreases of feature sizes in high-speed electronic´s circuits are limited by the increased parasitic effects of interconnect. This paper details the application of an on-chip time domain technique to the characterization of propagation delay, crosstalk and crosstalk-induced delay, along interconnects in deep submicron technology. The measurement system is detailed, together with the signal integrity patterns and their implementation in 0.18 CMOS technology. Measurement obtained with this technique are presented and compared with simulations.

Keywords

CMOS integrated circuits; high-speed integrated circuits; integrated circuit interconnections; integrated circuit testing; 0.18 micron; crosstalk; crosstalk-induced delay; deep submicron CMOS technology; high-speed electronic circuit; interconnect; microelectronic test structure; on-chip time domain measurement; parasitic effect; propagation delay; signal integrity; Bandwidth; CMOS technology; Circuit testing; Coupling circuits; Crosstalk; DH-HEMTs; Electronic circuits; Microelectronics; Propagation delay; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on

Print_ISBN

0-7803-6275-7

Type

conf

DOI

10.1109/ICMTS.2000.844407

Filename

844407