Title :
A differential floating gate capacitance mismatch measurement technique
Author :
Hunter, Jim ; Gudem, Prasad ; Winters, Steven
Author_Institution :
Cadence Design Syst. Inc., San Diego, CA, USA
Abstract :
This paper describes a differential floating gate capacitance matching measurement technique that offers a significant improvement in resolution over those previously reported. It´s smaller differential output voltage can be measured to a much higher precision than that of a standard structure. In addition, the differential technique offers superior cancellation of parasitic overlap capacitance effects. Our technique was successfully demonstrated on a 0.50 μm analog BiCMOS technology.
Keywords :
BiCMOS analogue integrated circuits; capacitance; integrated circuit measurement; integrated circuit testing; voltage measurement; analog BiCMOS technology; capacitance mismatch measurement technique; differential floating gate; differential output voltage; improved resolution; parasitic overlap capacitance effects; voltage measurement; Aging; BiCMOS integrated circuits; Capacitors; Measurement techniques; Parasitic capacitance; Signal resolution; Silicon; Testing;
Conference_Titel :
Microelectronic Test Structures, 2000. ICMTS 2000. Proceedings of the 2000 International Conference on
Print_ISBN :
0-7803-6275-7
DOI :
10.1109/ICMTS.2000.844421
