Characterization and modeling of LDMOS transistors on a 0.6 μm CMOS technology

High voltage integrated circuits (HVIC´s) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used high voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). The LDMOS transistor is based on the lightly doped drain concept. Two of the main objectives in designing LDMOS devices are to minimize the on-resistance while still maintaining a high breakdown voltage. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel into this region. This lightly doped drain region can have a large effect on the on-resistance, saturation current and feedback capacitance of the device. This paper presents a LDMOS device, considers some of the key specific parameters related to LDMOS devices, discusses a sub-circuit SPICE model implemented to model the LDMOS characteristics and investigates some interconnect metallization effects.