DocumentCode
2026588
Title
A method for determination of depletion width of single and double gate junction less transistor
Author
Deva Sarma, Kaushik Chandra ; Sharma, Santanu
Author_Institution
Dept. of Electron. & Commun., CIT, Kokrajhar, Kokrajhar, India
fYear
2015
fDate
29-30 Jan. 2015
Firstpage
114
Lastpage
119
Abstract
This paper presents a method for determining the depletion width of single and double gate Junction Less transistor. By solving 1D Poisson´s equation the depletion width expression is obtained. The variation of depletion width for both n-channel and p-channel device with doping concentration, gate voltage, drain to source voltage and dielectric constant of gate dielectric are shown.
Keywords
dielectric materials; permittivity; semiconductor doping; stochastic processes; transistors; 1D Poisson equation; depletion width expression; dielectric constant; doping concentration; double gate junction less transistor; drain voltage; gate dielectric; gate voltage; n-channel device; p-channel device; single gate junction less transistor; source voltage; Dielectric constant; Doping; Equations; Junctions; Logic gates; Transistors; Depletion Width; JLT; Poisson´s Equation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Computer Networks & Automated Verification (EDCAV), 2015 International Conference on
Conference_Location
Shillong
Print_ISBN
978-1-4799-6207-5
Type
conf
DOI
10.1109/EDCAV.2015.7060550
Filename
7060550
Link To Document