Analysis of asymmetric 3D DRAM architecture in combination with L2 cache size reduction

Memory is a heterogeneous complex in modern systems. Access time and bandwidth improvement of DRAM using die-stacking technology can only be evaluated by interacting with hardware components like underlying cache, CPU and software components like executed application and processed input. In this work we analyze encoding and decoding processes of JPEG2000 algorithm execution on MIPS I core for different picture sizes. Thereby we can observe that for picture sizes below particular critical value the DRAM share of execution time reaches max. 4%. Any DRAM improvement for this case would not lead to significant performance gain of whole system. Starting with particular picture size depending on last-level cache size the acceleration effect of cache falls off and DRAM influence rises up to 25% and remains for larger pictures. System-level estimation shows that our suggested 3D DRAM architecture can reduce that rise down to a third and is partially able to adopt cache functionality.