A framework for high-level synthesis of system on chip designs

Author

Stine, James E. ; Grad, Johannes ; Castellanos, Ivan ; Blank, Jeff ; Dave, Vibhuti ; Prakash, Mallika ; Iliev, Nick ; Jachimiec, Nathan

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA

fYear

2005

fDate

12-14 June 2005

Firstpage

67

Lastpage

68

Abstract

A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended for use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to be used for several AMI and TSMC technologies. Consequently, it is possible to fabricate student projects as well as do research in system on chip design through the MOSIS educational program. All steps in the design flow are fully automated with scripts and have been tested successfully in a large VLSI design class at the Illinois Institute of Technology.

Keywords

CMOS logic circuits; VLSI; circuit layout CAD; educational courses; electronic engineering education; high level synthesis; system-on-chip; AMI; Cadence Design Systems; Illinois Institute of Technology; MOSIS educational program; MOSIS scalable CMOS rules; SoC library; Synopsys; TSMC; VLSI design; electronic design automation tools; high-level synthesis; layout tools; scalable submicron rules; scripts; semi-custom designs; system on chip designs; CMOS technology; Circuits; Delay estimation; Educational programs; Energy management; Hardware; High level synthesis; Libraries; System-on-a-chip; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Systems Education, 2005. (MSE '05). Proceedings. 2005 IEEE International Conference on

Print_ISBN

0-7695-2374-9

Type

conf

DOI

10.1109/MSE.2005.8

Filename

1509366