Fine-grain pipelined asynchronous adders for high-speed DSP applications

Author

Singh, Montek ; Nowick, Steven M.

Author_Institution

Dept. of Comput. Sci., Columbia Univ., New York, NY, USA

fYear

2000

fDate

2000

Firstpage

111

Lastpage

118

Abstract

A new asynchronous pipeline scheme (called LP_w), and two new pipelined asynchronous adder implementations, are introduced for high-throughput applications such as DSPs for multimedia processing. The pipeline scheme is targeted to dynamic datapaths. A novelty of the approach is that it uses decoupled control for pull-up and pull-down stacks. The adders are pipelined at the gate-level and achieve very high throughput: 930-1023 million additions per second in a 0.6μ CMOS process. These results are expected to scale to several gigaoperations per second in more modern technologies

Keywords

CMOS digital integrated circuits; adders; asynchronous circuits; digital signal processing chips; multimedia computing; pipeline arithmetic; 0.6 micron; CMOS process; decoupled control; dynamic datapaths; fine-grain pipelined asynchronous adders; high-speed DSP applications; multimedia processing; pull-down stacks; pull-up stacks; throughput; Adders; Application software; CMOS process; Clocks; Computer science; Digital signal processing; Pipeline processing; Protocols; Strontium; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2000. Proceedings. IEEE Computer Society Workshop on

Conference_Location

Orlando, FL

Print_ISBN

0-7695-0534-1

Type

conf

DOI

10.1109/IWV.2000.844538

Filename

844538