Title :
A low-latency FIFO for mixed-clock systems
Author :
Chelcea, Tiberiu ; Nowick, Steven M.
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
Abstract :
This paper presents a low-latency FIFO design that interfaces subsystems on a chip working at different speeds. First, a single-clock domain design is introduced, which is then used as a basis for a mixed-clock version. Finally, the design is adapted to work between subsystems with very long interconnection delays. The designs can be made arbitrarily robust with regard to metastability and clock frequencies
Keywords :
CMOS memory circuits; asynchronous circuits; buffer storage; timing; FIFO design; interconnection delays; low-latency FIFO; mixed-clock systems; robust designs; Clocks; Computer science; Data buses; Delay; Hip; Metastasis; Postal services; Synchronization; Timing; Very large scale integration;
Conference_Titel :
VLSI, 2000. Proceedings. IEEE Computer Society Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7695-0534-1
DOI :
10.1109/IWV.2000.844540
