RT-level interconnect optimization in DSM regime

We propose global-net clustering based RT-level datapath design methodology. Static timing analysis identifies critical nets and critical primary input/output paths. Net clustering (based shared macro-cells and criticality) yields clusters wherein each cluster has strongly interdependent nets. Clusters and nets within every cluster are prioritized based on number of critical nets, number of nets, and the total macro-cell area. We propose two approaches to generate layouts at RTL: constructive (cluster growth) approach and iterative improvement based (simulated annealing) approach. For datapaths implemented in 0.35 μm technology, for both approaches, we achieved an average decrease of 54% in longest wirelength and 53% in overall wirelength