DocumentCode
2027127
Title
Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology
Author
Kuo, Hsin-Chih ; Yang, Chu-Yun ; Yeh, Jin-Fu ; Chuang, Huey-Ru ; Huang, Tzuen-Hsi
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2009
fDate
Sept. 29 2009-Oct. 1 2009
Firstpage
405
Lastpage
408
Abstract
A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of -8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.
Keywords
CMOS integrated circuits; microwave mixers; network topology; wireless LAN; CMOS process; WPAN applications; down-converting dual-gate mixer; dual-gate topology; frequency 60 GHz; power 16.8 mW; power 7.2 mW; power 9.6 mW; size 130 nm; CMOS technology; 130-nm; 60 GHz; CMOS; WPAN; dual-gate mixer;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference, 2009. EuMC 2009. European
Conference_Location
Rome
Print_ISBN
978-1-4244-4748-0
Type
conf
Filename
5296523
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