A Reduced Complexity Instruction Set architecture for low cost embedded processors

Implementing advanced DSP applications in software on a low power and low cost embedded RISC processors is a challenging task because of ISA shortcomings that inhibits performance. An embedded CISC processor can potentially deliver higher performance but not enough to meet the demand of complex DSP applications. We present a novel ISA that eliminates unnecessary overheads and speeds up the performance of embedded DSP applications on resource constrained processors. The implementation of the novel mixed ISA requires minor modification to the base architecture which translates to less than 5% increase in total power consumption. The novel ISA reduces the number of instructions used to implement a complex Fast Fourier Transform by less than half and speeds the processing by three folds leading to a substantial improvement in energy efficiency. Simulation results of a number of embedded benchmark programs show an average two fold increase in performance compared to a RISC processor.