An FPGA embedded system architecture for handwritten symbol recognition

This paper presents the design of an FPGA-based embedded system architecture for handwritten symbol recognition. The recognition algorithm is based on a self-organizing map neural network and was implemented on a Xilinx XC3S500E FPGA. The neural network operates on a set of chosen symbol features, rather than on the symbol image itself, in order to reduce memory requirements. The implemented system was tested as part of a hand-held calculator application, where an average recognition rate of 85 % was achieved for digit and mathematical symbol operators, which are entered on a touch screen by means of a stylus. The processing load demanded by the implementation is efficiently shared between soft-core processors and other digital logic blocks implemented on the same FPGA, thus employing minimal hardware resources.