• DocumentCode
    2028551
  • Title

    On-demand reconfiguration for coprocessors in mixed criticality multicore systems

  • Author

    Duy Viet Vu ; Sander, Oliver ; Sandmann, Timo ; Heidelberger, Jan ; Baehr, Steffen ; Becker, Juergen

  • Author_Institution
    Inst. of Inf. Process. Technol. (ITIV), Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
  • fYear
    2015
  • fDate
    20-24 July 2015
  • Firstpage
    569
  • Lastpage
    576
  • Abstract
    Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In a previous work, we proposed a concept that leverages the advantages of FPGA´s partial reconfiguration in heterogeneous mixed criticality multicore systems. The basic idea how to handle the partial reconfiguration transparently for noncritical tasks, while providing full control and a predictable behavior for safety relevant tasks was described. In this paper, we focus on the on-demand partial reconfiguration of coprocessors and its implementation details. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express, taking advantage of the Single-Root I/O Virtualization capabilities in modern PCI Express implementations. Experimental results show that compared to the reference software implementation, our concept achieves significantly shorter reconfiguration time with lower variance under various system load situations.
  • Keywords
    coprocessors; field programmable gate arrays; multiprocessing systems; peripheral interfaces; virtualisation; Intel multicore system; PCI Express; Xilinx Virtex-7 FPGA; coprocessors; mixed criticality multicore systems; on-demand partial reconfiguration; single-root I/O virtualization capabilities; Coprocessors; Field programmable gate arrays; Hardware; Multicore processing; Software; Virtual machining; Virtualization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing & Simulation (HPCS), 2015 International Conference on
  • Conference_Location
    Amsterdam
  • Print_ISBN
    978-1-4673-7812-3
  • Type

    conf

  • DOI
    10.1109/HPCSim.2015.7237094
  • Filename
    7237094