• DocumentCode
    2028703
  • Title

    Hardware Accelerators for Evolving Building Block Modules for Artificial Brains

  • Author

    De Garis, Hugo

  • Author_Institution
    Int. Sch. of Software, Wuhan Univ.
  • fYear
    2006
  • fDate
    15-18 June 2006
  • Firstpage
    222
  • Lastpage
    224
  • Abstract
    Summary form only given. This paper argues that it is technologically possible to build artificial brains at relatively low cost. The proposed approach to doing this is to evolve large numbers (tens of thousands) of neural network modules, each with its own simple function, and then interconnect them inside a computer that would execute the neural signaling of the whole brain in real time, performing functions such as controlling the behaviors of a robot. The modules could be configured automatically using evolutionary algorithms, by a successive reconfiguration on field programmable gate arrays (FPGA), placed on commercially available boards such as those offered by Celoxica. These chips could be programmed using high level languages, such as "Handel-C", whose statements are "hardware compiled" into the chip configuring instructions to wire up the chip, speeding-up the execution of instructions. The major challenge of this approach is architecting the artificial brain - how to put 10,000s of evolved neural net modules together to perform a library of controllable behaviors. One potential concern of this approach relates to the anticipated unwanted synergy of inter module neural signaling. While most current artificial brain projects use supercomputers or PC clusters with 1000s of nodes, Moore\´s law facilitates increasingly larger computational power at low costs, making brain building technically and economically possible. Examples from our efforts in evolving neural modules are presented, along with a critical analysis of the state of the art and realistic assessment of the challenges ahead
  • Keywords
    field programmable gate arrays; neural chips; FPGA; Moore law; artificial brain; evolutionary algorithm; field programmable gate array; hardware accelerator; high level language; neural network module; neural signaling; Artificial neural networks; Automatic control; Computer networks; Costs; Evolutionary computation; Field programmable gate arrays; Hardware; High level languages; Robotics and automation; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Adaptive Hardware and Systems, 2006. AHS 2006. First NASA/ESA Conference on
  • Conference_Location
    Istanbul
  • Print_ISBN
    0-7695-2614-4
  • Type

    conf

  • DOI
    10.1109/AHS.2006.50
  • Filename
    1638163