Accelerating a multiprocessor reconfigurable architecture with pipelined VLIW units

The X4CP32 is an architecture that combines the parallel and reconfigurable paradigms. It consists of a grid of reconfigurable and programming units (RPUs), each one containing 4 cells (including a microprocessor in each cell), responsible for all the processing and program flow. This paper presents architectural modifications in the X4CP32 in order to increase its performance. The RPU was implemented according to the VLIW (very long instruction word) methodology, and the cells were redesigned with a pipelined implementation. These improvements raised the maximum IPC of the RPU from 0.5 to 4 with an area overhead of 26%. To evaluate the new architecture, versions of the 2D discrete cosine transform, Montgomery modular multiplication and color space conversion were mapped, using the baseline architecture and the pipelined VLIW architecture.